With the increasing down-scaling of integrated circuits and increasing demanding requirements to the speed of integrated circuits, transistors need to have higher drive currents with increasingly smaller dimensions. Fin field-effect transistors (FinFETs) were thus developed. FIG. 1 illustrates a cross-sectional view of a conventional FinFET, wherein the cross-sectional view is made crossing the fins rather than the source and drain regions. Fins 100 are formed as vertical silicon fins extending above substrate 102 and are used to form source and drain regions (not shown) and channel regions therebetween. The formation of fins 100 include recessing substrate 102 to form recesses, filling the recesses with a dielectric material, performing a chemical mechanical polish (CMP) to remove excess portions of the dielectric material above fins 100, and recessing a top layer of the dielectric material, so that the remaining portions of the dielectric material in the recesses form shallow trench isolation (STI) regions 120. STI regions 120 typically comprise silicon oxide. Gate 108 is formed over fins 100. Gate dielectric 106 is formed to separate fins 100 from gate 108.
Parasitic capacitors 110 are generated between gate 108 and fins 100, wherein STI regions 120 act as the insulators of parasitic capacitors 110. The capacitance values of parasitic capacitors 110 are the functions of the shape of STI regions 120 and the materials (such as k values) of STI regions 120. The parasitic capacitance adversely affects the performance of the respective integrated circuit and needs to be reduced.